There are numerous manners in which to transfer data from a transmitter to a receiver. In a typical system for transferring data, a transmitter has clock circuitry that controls the speed at which data is transferred via a communications medium. A receiver in such a system also typically has clock circuitry that controls the speed at which the data that is received from the communications medium is processed.
Ideally, the receiver's clock and the transmitter's clock will operate at exactly the same frequency and will be appropriately aligned in phase. However, the clock used by the transmitter is typically different in phase and slightly different in frequency as compared to that of the receiver. Further, the data may be variably delayed through the transmission medium as well as through the receiver circuitry. For the case of transmission systems in which several transmitters are transmitting to one or more receivers (for instance, over a time-division multiplexed network), the receivers must recover each transmitter's clock and data, and therefore the receiver circuitry must be able to respond to any number of different phases and perhaps slightly different frequencies within a specified tolerance. Such a system in which data traveling along the transmission medium contains time-division-multiplexed “bursts” of data originating from transmitters with nearly the same clock frequency and no phase alignment is henceforth referred to as a “burst-mode” transmission system.
The efficiency of burst-mode systems is characterized by the ratio of a) the amount of time in the data stream occupied by the readable component of the data bursts, to b) the “unused” amount of time in the data stream comprised of inter-burst time gaps. To increase the efficiency of any burst-mode system, one seeks to reduce the time overhead introduced by the receiver circuitry and to minimize these inter-burst time gaps. In order to achieve the latter, all sources of delays in the transmission system must be accurately characterized and controlled. For instance, clock and data recovery (CDR) circuits may introduce timing delays due to slow synchronization when switching between bursts that prevent the efficient control and minimization of inter-burst time gaps. One method of addressing these efficiency and gap minimization problems is to measure the time delay and phase differences between the clock at the transmitter and the clock at the receiver. However, in order to measure this timing delay, it is necessary to know the characteristics of the clock at the transmitter, which is usually remote from the receiver. Therefore, some method of recovering the transmitter clock characteristics and associating those characteristics with the receiver clock and a particular data transmission is required.
Generally, in non-burst mode transmission systems CDR can easily be achieved by either standard open-loop or closed-loop clock recovery systems. Examples of these systems, which are well known in the art, are described in I. Dorros et al., An Experimental 224 Mb/s Digital Repeated Line, The Bell System Technical Journal, Vol. 45, No. 7, pp. 993–1043 (September 1966) and R. R. Cordell et al. in A 50 Mhz Phase- and Frequency-Locked Loop, IEEE Journal of Solid State Circuits, Vol. SC-14, No. 6, pp 1003–1010 (December 1979), respectively. Open-loop systems are characterized by a narrow bandpass filter (e.g., a SAW filter), while closed-loop systems typically contain a simple phase-locked loop, which attempts to lock onto the phase of the incoming signal. While such methods sufficiently recover clock and data for continuous or pseudo-bursty data, they are ineffective at CDR in burst mode systems. More recently, cost-effective methods and apparatus for recovering the phase of a signal in a burst-mode transmission system have been developed that avoid many of the deficiencies associated with prior apparatus and methods. One such method suited for use with burst mode signals generates a recovered clock more quickly than other methods in the prior art. This method is the subject of U.S. Pat. No. 5,237,290, issued on Aug. 17, 1993 to Mihai Banu et. al., which is hereby incorporated by reference herein in its entirety. Specifically, according to the '290 patent, the transmitter clock is recovered with a bounded phase relationship with respect to the incoming data signal. Thus, the recovered transmitter clock and the incoming data signal will have the same frequency and their relative phase will remain within a given range.
In another prior attempt, described in U.S. Pat. No. 5,757,872, issued on May 26, 1998 also to Mihai Banu et. al., a FIFO buffer was incorporated into the method of the '290 patent in order to prevent the loss of data that could result from the potential lack of synchronization between the local receiver clock and the recovered transmitter clock. The '872 patent is hereby incorporated by reference in its entirety herein.
Another prior attempt is described in copending U.S. patent application Ser. No. 10/255,008, which is hereby incorporated by reference in its entirety herein. In that attempt, the phase difference between the recovered transmitter clock associated with an incoming data word and the receiver clock was measured in order to capture and align the words of an incoming data stream. This phase difference, coupled with the measurement of time delays experienced in buffers associated with the receiver, were used to time the transmission of data from individual transmitters in the network with a maximum efficiency while, at the same time, preventing conflicts between successive data words transmitted by different transmitters.